A TRIZ Approach for Designing a Smart Lighting and Control System for Classrooms Based on Counter Application with Dual PIR Sensors.

Electrical energy is often wasted through human negligence when people do not switch off electrical appliances such as lighting after leaving a place. Such a scenario often happens in a classroom when the last person leaves the class and forgets to switch off the electrical appliances. Such wastage may not be able to be afforded by schools that are limited financially. Therefore, this research proposed a simple and cost-effective system that can analyze whether there is or is not a human presence in the classroom by applying a counter to count the total number of people entering and leaving the classroom based on the sensing signals of a set of dual PIR sensors only and then correlating this to automatically turn on or off the electrical appliances mentioned. The total number of people identified in the classroom is also displayed on an LCD screen. A TRIZ approach is used to support the ideation of the system. The system can switch on several electrical output loads simultaneously when the presence of people is detected and switch them off when there are no people in the classroom. The proposed system can be expanded to be used in homes, offices, and buildings to prevent the high cost of electricity consumption caused by the negligence of people. This enables smarter control of electricity consumption.

Energy-Efficient and Variability-Resilient 11T SRAM Design Using Data-Aware Read-Write Assist (DARWA) Technique for Low-Power Applications.

The need for power-efficient devices, such as smart sensor nodes, mobile devices, and portable digital gadgets, is markedly increasing and these devices are becoming commonly used in daily life. These devices continue to demand an energy-efficient cache memory designed on Static Random-Access Memory (SRAM) with enhanced speed, performance, and stability to perform on-chip data processing and faster computations. This paper presents an energy-efficient and variability-resilient 11T (E2VR11T) SRAM cell, which is designed with a novel Data-Aware Read-Write Assist (DARWA) technique. The E2VR11T cell comprises 11 transistors and operates with single-ended read and dynamic differential write circuits. The simulated results in a 45 nm CMOS technology exhibit 71.63% and 58.77% lower read energy than ST9T and LP10T and lower write energies of 28.25% and 51.79% against S8T and LP10T cells, respectively. The leakage power is reduced by 56.32% and 40.90% compared to ST9T and LP10T cells. The read static noise margin (RSNM) is improved by 1.94× and 0.18×, while the write noise margin (WNM) is improved by 19.57% and 8.70% against C6T and S8T cells. The variability investigation using the Monte Carlo simulation on 5000 samples highly validates the robustness and variability resilience of the proposed cell. The improved overall performance of the proposed E2VR11T cell makes it suitable for low-power applications.